The present invention relates to semiconductor design technology, and more particularly, to technology of generating a bit line equalizing signal to equalize a bit line pair of a semiconductor memory device.
A semiconductor memory device performs an internal amplifying process on data read out of a memory cell and transfers the amplified data, thereby outputting the data stored in the memory cell to the outside thereof. In general, the operation of amplifying the data of the memory cell is performed in a bit line amplifier (BLSA), and the BLSA performs the amplifying operation in response to an active command ACTIVE. In order to amplify data of another memory cell after amplifying data of a certain memory cell through the active operation, a precharge operation should be performed in response to a precharge command PRECHARGE prior to performing another active operation for the data of that other memory cell. Therefore, in order to enhance the performance of the semiconductor memory device, it is required to improve the speed of the precharge operation. That is, it is requited to improve performances such as row precharge or RAS precharge.
Particularly, it is important to improve the performance of the operation of equalizing a bit line pair connected to memory cells among several internal operations performed during the RAS precharge. The operation of equalizing the bit line pair is an operation of setting the bit line pair to an identical potential level, and a precharge voltage having a certain potential level is used for the equalizing operation.
FIG. 1 illustrates a diagram of a conventional semiconductor memory device.
Referring to FIG. 1, the semiconductor memory device includes a memory cell 110, a bit line equalizing unit 120 for equalizing a bit line pair BL and BLB, a bit line equalizing signal generating unit 130 for generating a bit line equalizing signal BLEQ to control the bit line equalizing unit 120, a bit line amplifying unit 140 for amplifying data of the memory cell 110, and a bit line amplification driving unit 150 for controlling the bit line amplifying unit 140. For the reference, FIG. 1 shows one memory cell of the semiconductor memory device, but practically the semiconductor memory device includes an array constructed by a plurality of memory cells connected to a word line WL and a bit line BL.
Herein, the memory cell 110 includes a cell capacitor C for storing the data and a cell transistor MN0, wherein the cell transistor MN0 includes one end N1 connected to the bit line BL, the other end N2 connected to the cell capacitor C, and a gate G connected to the word line WL.
The bit line equalizing unit 120 includes NMOS transistors MN1, MN2 and MN3 to supply a precharge voltage VBLP to the bit line pair BL and BLB. As a semiconductor memory device is highly integrated and miniaturized, it is difficult to secure a region where the bit line equalizing unit 120 is disposed since the bit line equalizing unit 120 is disposed in a narrow region between memory cells. As a result, it is also difficult to secure a desired width of the NMOS transistors constructing the bit line equalizing unit 120. Thus, in order to improve the operating speed of the bit line equalizing unit 120 having a limited size, it is required to raise the potential level of the bit line equalizing signal BLEQ controlling the NMOS transistors MN1, MN2 and MN3 of the bit line equalizing unit 120. However, the raising of the potential level of the bit line equalizing signal BLEQ results in increasing power consumption in the bit line equalizing signal generating unit 130.
The semiconductor memory device illustrated in FIG. 1 operates as follows.
FIG. 2 describes a timing diagram for an operation of the semiconductor device illustrated in FIG. 1.
Referring to FIG. 2, an enable signal EN is enabled as a high level signal in response to an active signal, and disabled as a low level signal in response to a precharge signal. The enable signal EN has the high level during an active period. If the enable signal EN is enabled as the high level, a word line enable signal WL is enabled as a high level and a cell transistor MN0 is turned on. Thus, the data stored in the cell capacitor C is transferred onto the bit line BL. Since the data transferred onto the bit line BL has a weak signal level, the bit line amplification driving unit 150 transfers a bit line amplifying signal SAEN enabled as a high level to the bit line amplifying unit 140, and the bit line amplifying unit 140 amplifies the data on the bit line BL and outputs the amplified data to the bit line pair BL and BLB. In general, the bit line amplifying unit 140 is constructed with a cross-coupled differential amplifier whose input terminals are connected to the bit line pair BL and BLB.
Meanwhile, the bit line equalizing signal BLEQ transits to a low level so as to inactivate the bit line equalizing unit 120 during the active operation. On the other hand, the bit line equalizing signal BLEQ transits to a high level so as to activate the bit line equalizing unit 120 during the precharge operation. The activated bit line equalizing unit 120 equalizes voltage levels of the bit line pair BL and BLB to the precharge voltage level VBLP.
In the prior art, in order to improve a bit line equalizing speed, the bit line equalizing signal generating unit 130 drives its output terminal with a pumping voltage having a higher potential level than that of an external supply voltage and the bit line equalizing signal BLEQ provided through the output terminal of the bit line equalizing signal generating unit 130 is used to control the bit line equalizing unit 120. However, this technique has a disadvantage of increasing current consumption required to transfer the bit line equalizing signal BLEQ. Moreover, the pumping voltage obtained by boosting the external supply voltage has very low efficiency and, thus, the current consumption is substantially increased as the time using the pumping voltage becomes longer. Compared to the case of using the external supply voltage, a longer time is required in dropping the bit line equalizing signal BLEQ having the pumping voltage level to a ground voltage level and, thus, an inactivation time of the bit line equalizing unit 120 is delayed in the active operation. This means that an activation time of the word line WL should be delayed as much as the delay of the inactivation time of the bit line equalizing unit 120, thereby performing a stabilized amplifying operation. As a result, there is produced a side effect which a processing time of the active operation becomes much longer.